1. Field of the Invention
The present invention relates to a process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection.
Though applicable to EPROM, EEPROM and flash-EEPROM memories, the present invention is particularly advantageous in the case of flash-EEPROMs to which special reference is made in the following description.
2. Discussion of the Related Art
Flash-EEPROM memories are Electrically Era-sable Programmable Read Only Memories (EEPROMS), which combine the high density and low cost of EPROMs with the advantage of electrical erasability. They have recently become the most attractive of nonvolatile memories for their potential application in solid state disks for portable computers.
Though various flash memory concepts have been developed, most manufacturers employ double-poly single-transistor cells with a structure closely resembling that of standard EPROM cells. Flash-EEPROM memory cells comprise an NMOS transistor with a polysilicon floating gate region capacitively coupled to a polysilicon or polycide (polysilicon and silicide) control gate region. The main difference between EEPROM and flash-EEPROM memories lies in the thickness of the oxide between the floating gate region and the substrate, which is thinner in the case of flash cells.
The yield and reliability of flash memories are known to be closely related to the of the tunnel oxide, which quality not only depends on preoxidation cleaning and the oxidation process itself, but is also strongly affected by the post-oxidation process steps.
Of all the process steps, the most critical are those which expose the wafer to radiation damage, namely ion implantation, plasma etching, sputtering and plasma enhanced chemical vapour deposition.
Currently used flash-EEPROM memory processes present a large number of such steps following growth of the tunnel oxide.
The model generally accepted for explaining in-process radiation is the so-called "antenna effect" in which charges are trapped in conductive layers and may result in a critical increase in the potential of the layers.
To explain the phenomenon, it should be borne in mind that ion implantation and plasma processes involve the collision of charged particles (either electrons or ions) with the wafer surface, so that conductive polysilicon layers insulated from the silicon substrate may be charged by capturing the charged particles.
If the polysilicon layer is not patterned, it acts as an electrostatic shield. In fact, the charge is distributed evenly over the entire area of the wafer, thus generating a low electric field. This is also because, in the case of ion implantation, the beam is localized and the overall charge density is low. In addition the metal grips holding the wafer may act as discharge lines for at least partly removing the captured charged particles, so that little danger exists f or the dielectric layer underlying the polysilicon.
If, on the other hand, the layer is patterned and comprises "islands", i.e., areas insulated conductively from the rest of the layer and separated from the substrate by a thin oxide layer, as in the case of gate regions, the layer is charged to a potential that depends on the collecting area and its capacity versus the substrate, i.e., the area of the thin oxide. 1-f the ratio between the collecting area and the area of the thin oxide is unfavourable (high), the gate region may easily reach a potential higher than the breakdown voltage of the thin oxide, thus resulting in oxide breakdown--in turn, resulting in "zero time" device failure, i.e. before it is even used--or in oxide damage with the formation of traps in the oxide itself and which, in turn, results in "latent" device failure and impaired reliability. The above model also applies to flash cells. In fact, in certain situations, the tunnel oxide may be damaged due to capacitive coupling of the control and floating gate regions, and the lower dielectric resistance of the tunnel oxide in relation to the dielectric layer separating the control and floating gates. The likelihood of this occurring is even greater, in view of the extensive collecting area defined by the polysilicon strips forming the control gates, and the small area of the tunnel oxide of each cell. Consequently, the tunnel oxide may be broken or damaged in the event the control gate region is charged to a potential greater than the breakdown voltage of the tunnel oxide divided by the coupling factor of the control gate.
It is an object of the present invention to provide a process for fabricating integrated devices with protection of the thin tunnel oxide layer of the memory cells, and which provides for exploiting the basic principle and technical advantages of the DPCC process, described below.